By Anant G Sabnis
As built-in cicuits develop into extra advanced, with smaller and smaller geometries, even more care needs to be taken to prevent reliability difficulties. This sensible quantity covers a extensive spectrum of reliability matters in built-in circuits, from simple techniques to packaging.
Topics include:**failure research techniques**radiation effects**reliability insurance and qualification
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At wafer level the damage affects the yield. If the d a m a g e o c c u r s after the chips are packaged, the cost increases to a few dollars per package (depending on the type of IC). T h e cost may increase by an o r d e r of magnitude if the E S D d a m a g e o c c u r s at the printed circuit board level. T w o o r three orders of magnitude higher costs m a y b e incurred w h e n the d a m a g e o c c u r s after the system is commissioned at the u s e r ' s site. In practice, the cost of repair can a m o u n t to t h o u s a n d s of dollars.
A simple circuit that uses this principle is illustrated in Fig. 2a. T h e circuit s h o w n in Fig. 2b is a modification of Fig. 2a with resistors R\ and R2 a d d e d in the path of the input pulse. T h e p u r p o s e of resistance R\ is to limit the cur rents through diodes Di and D2 when they are forward-biased, and the resistor R2 helps delay the E S D pulse by introducing an RC time c o n s t a n t before it reaches the gate of the active transistor T. 4. On-Chip Protection 9VDD A Dl D2 Vss (a) Η Γ (b) Fig.
EOS/ ESD Symp. Proc, Vol. E O S - 3 , pp. 85-89 (1981). L. F. DeChiaro, Device Susceptibility Testing and Design Hardening. EOS/ESD Symp. Proc, Vol. EOS-6, pp. 179-188 (1984). C. Duvvury, R. N. Rountree, D. A. Baglee, R. A. McPhee, A. E. Hyslop, and L. S. White, ESD Design Considerations for VLSI. EOS/ESD Symp. Proc, Vol. E O S - 7 , pp. 45-48 (1985). A. R. Palella and H. Domingos, A Design Methodology for ESD Protection Networks. EOS/ESD Symp. Proc, Vol. EOS-7, pp. 25-39 (1985). K. J. Orlowsky, D.