Embedded Memory Design for Multi-Core and Systems on Chip by Baker Mohammad

By Baker Mohammad

This ebook describes some of the tradeoffs platforms designers face whilst designing embedded reminiscence. Readers designing multi-core structures and platforms on chip will enjoy the dialogue of other issues from reminiscence structure, array association, circuit layout suggestions and layout for try. The presentation permits a multi-disciplinary method of chip layout, which bridges the space among the structure point and circuit point, to be able to deal with yield, reliability and power-related matters for embedded memory.

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For a CAM-based tag, the cache banking must be based on the index in order to store all the contents of a cache line, with its respective CAM entry. Additionally, all 16 cache lines for each set must be stored in the same bank to ensure that only a single set of CAM comparators is activated. Overall, these requirements allow for less flexibility in the organization of the CAM-based cache. Moreover, since the L1 in our case is pseudo-dual ported, keeping the entire cache line in one set of a bank is important for minimizing bank conflicts.

1 Data Arrays Banking Options Banking by way: In this option data arrays are divided into equal sections with each section containing all sets from the same way. In our example we will have eight sections for L1 one for each way that contains 128 × 256 bits of memory or 4 KB. The next level of details is how to organize this 4 KB into banks. The simplest way is to have one bank with 128 entries and 256 bits which means an array of 128 rows and 256 columns. Other options are to have multiple banks per way.

1007/978-1-4614-8881-1_4, © Springer Science+Business Media New York 2014 37 4 SRAM-Based Memory Operation and Yield 38 WL Vddmem PU2 BLB BL I2 PD2 n1 n2 PG1 I3 PU1 I0 PG2 Cn1 Cn2 PD1 C2 C1 I1 Fig. 1 SRAM Cell Stability The SRAM cell is a regenerative bistable circuit. When the cell is accessed, its content is expected to stay the same. 1 illustrates the 6T SRAM cell with wordline node controlling the access transistors; n1 and n2 are the internal nodes, and BL and BLB are the bitlines of the cell.

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