Designing Embedded Network Applications Essential Insights by Gerard Hartnett, Peter Barry

By Gerard Hartnett, Peter Barry

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Caches use these attributes to identify how to handle a transaction appropriately. Information is supplied to the MMU controller in the form of a translation table. The translation table base register (Co-processor 15—register 2) points to the physical address of the first-level translation table. The translation table consists of 4000 first-level descriptors and optionally second-level descriptors. Descriptors provide information on the address translation, access permissions, and caching options for a range of physical memory addresses to the MMU.

Frequent TLB misses degrade the performance of the application. A table of 16 kilobytes fully describes memory in 1-megabyte blocks using section entries in the page table, whereas a table of approximately 16 megabytes is needed to fully describe memory using tiny pages. The operating system typically defines the granularity of page tables used. 4 shows a section translation of a virtual address to a physical address. This type of translation is the simplest. The translation replaces bit 20 to bit 31 of the virtual address, with the section base address (bit 20 to bit 31) read from the MMU table to produce the physical address.

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