By Bart Vermeulen, Kees Goossens (auth.)
This e-book describes an procedure and helping infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), permitting its linked product to be brought into the industry extra speedy. Readers research step by step the main requisites for debugging a latest, silicon SOC implementation, 9 components that complicate this debugging activity, and a brand new debug process that addresses those standards and complicating components. The authors’ novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug strategy is mentioned intimately, displaying the way it is helping to satisfy debug specifications and handle the 9, formerly pointed out elements that complicate debugging silicon implementations of SOCs. The authors additionally derive the debug infrastructure specifications to help debugging of a silicon implementation of an SOC with their CSAR debug method. This debug infrastructure contains a popular on-chip debug structure, a configurable automatic design-for-debug circulate for use throughout the layout of an SOC, and customizable off-chip debugger software program. insurance comprises an evaluate of the potency and effectiveness of the CSAR technique and its assisting infrastructure, utilizing six commercial SOCs and an illustrative, instance SOC version. The authors additionally quantify the expense and layout attempt to help their approach.
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Extra info for Debugging Systems-on-Chip: Communication-centric and Abstraction-based Techniques
1 test access port (TAP), – we introduce the guided replay process at the communication level between building blocks, and – we use structural, data, behavioral, and temporal abstraction techniques to the scan chain contents to abstract all the way up to the level of the application with multiple distributed masters and slaves. • We provide a customizable, scalable, and layout-friendly, on-chip debug architecture to support our CSAR debug approach. This debug architecture provides control over the on-chip communication and allows the extraction of globallyconsistent state information from the SOC via an IEEE Std.
Jack Browne. 318 engineers surveyed on top core frequencies and noc use issues, November 2012. 6. Theo A. C. M. Claasen. System on a chip: Changing ic design today and in the future. IEEE Micro, 23(3):20–26, May 2003. 7. A. Danial. Cloc - count lines of code, 2012. 8. Giovanni De Micheli and Luca Benini, editors. Networks on Chips: Technology and Tools. The Morgan Kaufmann Series in Systems on Silicon. , July 2006. 9. Harry Foster. Wilson research group and mentor graphics, 2012 functional verification study.
1 A high-level overview of trace-based and run/stop-based debug approaches Characteristic Trace-based approach Run/stop-based approach Spatial scope Temporal scope Hardware support Subset of internal signals At multiple points during the execution Trigger mechanism On-chip memory Data output port Configuration mechanism Real-time, internal observability All internal signals At the end of the execution Trigger mechanism Execution stop mechanism State access mechanism Configuration mechanism Full internal observability Full internal controllability Non-real-time Silicon area cost Main advantages Disadvantages Subset relatively very small Silicon area cost The post-silicon debug process involves observing and analyzing the erroneous behavior of a silicon implementation in the environment in which it fails.