Counting and Counters by R. M. M. Oberman (auth.)

By R. M. M. Oberman (auth.)

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Additional info for Counting and Counters

Sample text

The fundamental circuit of this counter has already been discussed with the help of figure 2-2. The same principle has been used in the SN74LS168A BCD up-down counter. [2] The SN74Sl68 and SN74S169 counters are examples of the second type with separate add-l and subtract-l gate circuits for the up- and down-counting operation. The two networks are rather difficult to recognise in the manufacturer's diagram. These networks are given he re in figure 2-20. The configuration of some gates has been rearranged so that the characteristic features of both networks can be recognized more easily.

The count-up and the count-down pulses are not given simultaneously. at:ffi;:::a==ill::h:;:::::b--jJJ-r-J, Figure 2-21 Up-down counter control circuit, two pulse sources respectively the add-1 and the subtract-l gate circuits. The add-l network consists of AND gates 3, 6 and 9, the subtract-1 network ofAND gates 2, 5 and 8. The up· and down-counting pulses can control in a ripple-through operation a similar more significant 4-bit counter via output AND gates 11 and 12. It would have been possible to avoid the double network controlling the flipflops, but this would have disturbed the complete symmetrical circuit for up- and down-count.

PT AND input gates 5 show the fusion of the P and T signals into one enable ei signal. 4 SPECIAL FORMS OF BINARY COUNTER Binary-decimal counters Decades of a decimal counter can be obtained by limiting the counting cyde of a 4-bit binary counter to ten. This limitation can be obtained in two practical ways. (i) The first ten 4-bit binary code words are used, so that the counter runs from o to 9, returns to zero on the tenth pulse, and generates a carry pulse to the next decimal section of the counter.

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