Circuit Techniques for Low-Voltage and High-Speed A/D by Mikko E. Waltari

By Mikko E. Waltari

The expanding digitalization in all spheres of electronics functions, from telecommunications structures to client electronics home equipment, calls for analog-to-digital converters (ADCs) with a better sampling price, better answer, and reduce energy intake. The evolution of built-in circuit applied sciences partly is helping in assembly those specifications via supplying swifter units and taking into account the conclusion of extra advanced capabilities in a given silicon region, yet concurrently it brings new demanding situations, an important of that's the lowering provide voltage. in accordance with the switched capacitor (SC) strategy, the pipelined structure has so much effectively exploited the positive factors of CMOS expertise in knowing high-speed high-resolution ADCs. An research of the consequences of the provision voltage and expertise scaling on SC circuits is conducted, and it exhibits that advantages will be anticipated at the very least for the following couple of expertise generations. The operational amplifier is a important development block in SC circuits, and therefore a comparability of the topologies and their low voltage services is gifted. it's recognized that the SC process in its commonplace shape isn't compatible for terribly low offer voltages, customarily as a result of inadequate swap keep an eye on voltage. low-voltage changes are investigated: change bootstrapping and the switched opamp (SO) approach. enhanced circuit constructions are proposed for either. ADC prototypes utilizing the SO strategy are awarded, whereas bootstrapped switches are used in 3 different prototypes. an essential component of an ADC is the front-end sample-and-hold (S/H) circuit. At excessive sign frequencies its linearity is predominantly decided through the switches applied. A evaluation of S/H architectures is gifted, and turn linearization via bootstrapping is studied and utilized to 2 of the prototypes. one other vital parameter is sampling clock jitter, that's analyzed after which minimized with carefully-designed clock new release and buffering. The throughput of ADCs could be elevated by utilizing parallelism. this can be validated at the circuit point with the double-sampling approach, that is utilized to S/H circuits and a pipelined ADC. An research of nonidealities in double-sampling is gifted. on the procedure point parallelism is used in a time-interleaved ADC. The mismatch of parallel sign paths produces mistakes, for the removal of which a timing skew insensitive sampling circuit and a electronic offset calibration are constructed. Circuit thoughts for Low-Voltage and High-Speed A/D Converters offers a complete of 7 prototypes: double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a present steerage DAC with a deglitcher, and pipelined ADCs utilizing the SO options. This monograph will turn out to be an invaluable reference for either teachers and pros whom are lively within the Analog Circuit layout and Communications box.